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field-programmable gate array (fpga) platforms  (Xilinx Inc)

 
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    Xilinx Inc field-programmable gate array (fpga) platforms
    Field Programmable Gate Array (Fpga) Platforms, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
    https://www.bioz.com/product/field-programmable+gate+array+(fpga)+platforms/programmable+gate+array/pmc09505044-92-16-15
    Average 90 stars, based on 1 article reviews
    field-programmable gate array (fpga) platforms - by Bioz Stars, 2026-09
    90/100 stars

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    Related Articles

    Blocking Assay:

    Article Title: RRSC-128/64-V1: a two-variant simple, fast, and secure lightweight stream cipher
    Article Snippet: Lightweight cryptography is now emerging as a new method for providing security to resource-constrained devices.. Securing those devices from external hackers during data transmission is now becoming an important issue.. This paper proposed a lightweight simple stream cipher which provides security and confidentiality of the data among resource-constrained devices.

    Article Title: Implement-on-ground detection using vibration signals
    Article Snippet: For example, one or more elements of computer system 1100 may be implemented as a field-programmable gate array (FPGA), such as those commercially available by XILINX®, INTEL®, or LATTICE SEMICONDUCTOR®, a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a microcontroller, and/or a hybrid device, such as an SoC FPGA, among other possibilities.

    Article Title: An effective lossless compression method for attitude data with implementation on FPGA.
    Article Snippet: By using real-world drilling data, the proposed method is implemented on a Verilog HDL on a Xilinx fieldprogrammable gate array (FPGA) circuit.

    Article Title: Entity resolution in genealogical databases
    Article Snippet: For example, one or more elements of the computer system 1000 (or the device 1001) may be implemented as a field-programmable gate array (FPGA), such as those commercially available by XILINX®, INTEL®, or LATTICE SEMICONDUCTOR®, a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a microcontroller, and/or a hybrid device, such as an SoC FPGA, among other possibilities.

    Article Title: A lightweight algorithm for synchronized multimodal data acquisition using temporal sample alignment
    Article Snippet: The authors of the paper used reconfigurable hardware technology from a Xilinx ® field-programmable gate array (FPGA) to implement their time synchronization algorithms.

    Article Title: Efficient Real-Time Isotope Identification on SoC FPGA.
    Article Snippet: The first algorithm, PCA, is efficiently accelerated in the programmable logic of the FPGA, while the classifier runs on the ARM processor that is included in the selected SoC FPGA (AMD Xilinx ZC706).

    Article Title: An effective lossless compression method for attitude data with implementation on FPGA
    Article Snippet: By using real-world drilling data, the proposed method is implemented on a Verilog HDL on a Xilinx field-programmable gate array (FPGA) circuit.

    Article Title: Design and Application of a Radiofrequency Spectrophotometry Sensor for Measuring Esophageal Liquid Flow to Detect Gastroesophageal Reflux
    Article Snippet: This board is based on a field-programmable gate array (FPGA) SoC Zynq 7010 from Xilinx, which has a programmable logic zone of 28,000 logic cells together with which a dual-core Cortex-A9 microprocessor is integrated.



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    Image Search Results


    Comparison of the FPGA implementation BER for M = 4 , 3RC, h = { 4 16 , 5 16 } , and h = { 5 16 , 6 16 } , h = { 9 16 , 10 16 } CPM schemes.

    Journal: Entropy

    Article Title: Design and Implementation of a Low-Complexity Multi- h CPM Receiver with Linear Phase Approximation Synchronization Algorithm

    doi: 10.3390/e25111530

    Figure Lengend Snippet: Comparison of the FPGA implementation BER for M = 4 , 3RC, h = { 4 16 , 5 16 } , and h = { 5 16 , 6 16 } , h = { 9 16 , 10 16 } CPM schemes.

    Article Snippet: We implement the overall receiver for the above three multi- h CPM schemes with LPA-based synchronization and MLSD on a Xilinx Kintex-7 field-programmable gate array (FPGA) platform.

    Techniques: Comparison

    FPGA implementation complexity comparison.

    Journal: Entropy

    Article Title: Design and Implementation of a Low-Complexity Multi- h CPM Receiver with Linear Phase Approximation Synchronization Algorithm

    doi: 10.3390/e25111530

    Figure Lengend Snippet: FPGA implementation complexity comparison.

    Article Snippet: We implement the overall receiver for the above three multi- h CPM schemes with LPA-based synchronization and MLSD on a Xilinx Kintex-7 field-programmable gate array (FPGA) platform.

    Techniques: Comparison, Blocking Assay

    ( a ) Block diagram of the experimental setup which consists of a stack of three boards: a daughter board with the design CHIP, a motherboard which meanly provides the power supply, and the USB2 interface and a commercial FPGA design kit. ( b ) Picture of the experimental setup.

    Journal: Sensors (Basel, Switzerland)

    Article Title: Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout

    doi: 10.3390/s21123949

    Figure Lengend Snippet: ( a ) Block diagram of the experimental setup which consists of a stack of three boards: a daughter board with the design CHIP, a motherboard which meanly provides the power supply, and the USB2 interface and a commercial FPGA design kit. ( b ) Picture of the experimental setup.

    Article Snippet: In order to characterize the prototype, a testing platform based on Field Programmable Gate-Array (FPGA) DE10NANO (Terasic Inc., Hsinchu City, Taiwan) board was developed as shown in .

    Techniques: Blocking Assay

    Last FPA request timing measurement. ( a ) Internal acknowledge mode with an output cycle of only 3 ns. ( b ) External acknowledge mode with an output cycle of 56 ns limited by the FPGA operating frequency.

    Journal: Sensors (Basel, Switzerland)

    Article Title: Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout

    doi: 10.3390/s21123949

    Figure Lengend Snippet: Last FPA request timing measurement. ( a ) Internal acknowledge mode with an output cycle of only 3 ns. ( b ) External acknowledge mode with an output cycle of 56 ns limited by the FPGA operating frequency.

    Article Snippet: In order to characterize the prototype, a testing platform based on Field Programmable Gate-Array (FPGA) DE10NANO (Terasic Inc., Hsinchu City, Taiwan) board was developed as shown in .

    Techniques: