Journal: Micromachines

Article Title: Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device

doi: 10.3390/mi14030611

Figure Lengend Snippet: ( a ) The top view of the simulated three-layer stacked nanosheets transistor schematic; ( b ) cross-sectional view of stress distribution under different process steps in Sentaurus.

Article Snippet: The S/D regions with varied length from 0.2 μm to 2.0 μm and a fixed width of 1 μm were used, while the same nanosheets width of 30 nm and length 100 nm were adopted. a displays the comparison of stress in the bottom sheets calculated by Sentaurus and COMSOL.

Techniques:

Journal: Micromachines

Article Title: Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device

doi: 10.3390/mi14030611

Figure Lengend Snippet: ( a ) The stress values calculated by Sentaurus and COMSOL and displacement in bottom nanosheet channel as a function of varied S/D region length. GAA device with different S/D length ( b ) 0.5 µm and ( c ) 2 µm schematics of displacement mapping of top, middle and bottom nanosheet in COMSOL (Si nanosheet length: 100 nm width: 30 nm). ( d ) Extracted displacement of bottom nanosheet along XX direction with S/D region length 0.5 µm and 2 µm.

Article Snippet: The S/D regions with varied length from 0.2 μm to 2.0 μm and a fixed width of 1 μm were used, while the same nanosheets width of 30 nm and length 100 nm were adopted. a displays the comparison of stress in the bottom sheets calculated by Sentaurus and COMSOL.

Techniques: