Structured Review

Intel ssvfilter
Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on <t>SSVFilter</t>
Ssvfilter, supplied by Intel, used in various techniques. Bioz Stars score: 90/100, based on 420 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/ssvfilter/product/Intel
Average 90 stars, based on 420 article reviews
Price from $9.99 to $1999.99
ssvfilter - by Bioz Stars, 2020-08
90/100 stars

Images

1) Product Images from "CUDAMPF: a multi-tiered parallel framework for accelerating protein sequence search in HMMER on CUDA-enabled GPU"

Article Title: CUDAMPF: a multi-tiered parallel framework for accelerating protein sequence search in HMMER on CUDA-enabled GPU

Journal: BMC Bioinformatics

doi: 10.1186/s12859-016-0946-4

Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on SSVFilter
Figure Legend Snippet: Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on SSVFilter

Techniques Used:

2) Product Images from "CUDAMPF: a multi-tiered parallel framework for accelerating protein sequence search in HMMER on CUDA-enabled GPU"

Article Title: CUDAMPF: a multi-tiered parallel framework for accelerating protein sequence search in HMMER on CUDA-enabled GPU

Journal: BMC Bioinformatics

doi: 10.1186/s12859-016-0946-4

Illustrations of proposed reordering and maximum functions for CUDAMPF. Assuming x 4 > x 3 > x 2 > x 1 after intra-warp reductions in ( b )
Figure Legend Snippet: Illustrations of proposed reordering and maximum functions for CUDAMPF. Assuming x 4 > x 3 > x 2 > x 1 after intra-warp reductions in ( b )

Techniques Used:

Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on ViterbiFilter
Figure Legend Snippet: Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on ViterbiFilter

Techniques Used:

CUDAMPF program with NVRTC. After obtaining query model size and device properties, program dynamically makes decisions on unrolling innermost loop and selects the proper kernel file with compiler options
Figure Legend Snippet: CUDAMPF program with NVRTC. After obtaining query model size and device properties, program dynamically makes decisions on unrolling innermost loop and selects the proper kernel file with compiler options

Techniques Used:

Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on SSVFilter
Figure Legend Snippet: Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on SSVFilter

Techniques Used:

Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on MSVFilter
Figure Legend Snippet: Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on MSVFilter

Techniques Used:

CUDAMPF: Multi-tiered Parallel Framework on CUDA-enabled GPU. ( a ) A single GPU consists of n SMXs with m concurrently mounted blocks on each; ( b ) within each block, q resident warps are scheduled by x warp scheduler for processing assigned sequences; ( c ) a warp of threads score alignment of all residues and model states in parallel (warp size is fixed to 32 currently); ( d ) based on 32-bit register and score ranges of different algorithms, each thread processes multiple model states in a single step. The virtual boundary, block , is only regarded as the container of warps rather than a separate tier
Figure Legend Snippet: CUDAMPF: Multi-tiered Parallel Framework on CUDA-enabled GPU. ( a ) A single GPU consists of n SMXs with m concurrently mounted blocks on each; ( b ) within each block, q resident warps are scheduled by x warp scheduler for processing assigned sequences; ( c ) a warp of threads score alignment of all residues and model states in parallel (warp size is fixed to 32 currently); ( d ) based on 32-bit register and score ranges of different algorithms, each thread processes multiple model states in a single step. The virtual boundary, block , is only regarded as the container of warps rather than a separate tier

Techniques Used: Blocking Assay

3) Product Images from "CUDAMPF: a multi-tiered parallel framework for accelerating protein sequence search in HMMER on CUDA-enabled GPU"

Article Title: CUDAMPF: a multi-tiered parallel framework for accelerating protein sequence search in HMMER on CUDA-enabled GPU

Journal: BMC Bioinformatics

doi: 10.1186/s12859-016-0946-4

CUDAMPF: Multi-tiered Parallel Framework on CUDA-enabled GPU. ( a ) A single GPU consists of n SMXs with m concurrently mounted blocks on each; ( b ) within each block, q resident warps are scheduled by x warp scheduler for processing assigned sequences; ( c ) a warp of threads score alignment of all residues and model states in parallel (warp size is fixed to 32 currently); ( d ) based on 32-bit register and score ranges of different algorithms, each thread processes multiple model states in a single step. The virtual boundary, block , is only regarded as the container of warps rather than a separate tier
Figure Legend Snippet: CUDAMPF: Multi-tiered Parallel Framework on CUDA-enabled GPU. ( a ) A single GPU consists of n SMXs with m concurrently mounted blocks on each; ( b ) within each block, q resident warps are scheduled by x warp scheduler for processing assigned sequences; ( c ) a warp of threads score alignment of all residues and model states in parallel (warp size is fixed to 32 currently); ( d ) based on 32-bit register and score ranges of different algorithms, each thread processes multiple model states in a single step. The virtual boundary, block , is only regarded as the container of warps rather than a separate tier

Techniques Used: Blocking Assay

4) Product Images from "GLIMMPSE: Online Power Computation for Linear Models with and without a Baseline Covariate"

Article Title: GLIMMPSE: Online Power Computation for Linear Models with and without a Baseline Covariate

Journal: Journal of statistical software

doi:

GLIMMPSE results screen.
Figure Legend Snippet: GLIMMPSE results screen.

Techniques Used:

GLIMMPSE mode selection screen.
Figure Legend Snippet: GLIMMPSE mode selection screen.

Techniques Used: Selection

3.2. How to use GLIMMPSE
Figure Legend Snippet: 3.2. How to use GLIMMPSE

Techniques Used:

Overview of the GLIMMPSE architecture.
Figure Legend Snippet: Overview of the GLIMMPSE architecture.

Techniques Used:

5) Product Images from "GPU Acceleration of Optical Mapping Algorithm for Cardiac Electrophysiology"

Article Title: GPU Acceleration of Optical Mapping Algorithm for Cardiac Electrophysiology

Journal: Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Conference

doi: 10.1109/EMBC.2012.6346240

The performance of the GPU implementation in comparison to the Matlab CPU implementation, the serial C++ implementation and the OpenMP C++ implementation.
Figure Legend Snippet: The performance of the GPU implementation in comparison to the Matlab CPU implementation, the serial C++ implementation and the OpenMP C++ implementation.

Techniques Used:

6) Product Images from "CUDAMPF: a multi-tiered parallel framework for accelerating protein sequence search in HMMER on CUDA-enabled GPU"

Article Title: CUDAMPF: a multi-tiered parallel framework for accelerating protein sequence search in HMMER on CUDA-enabled GPU

Journal: BMC Bioinformatics

doi: 10.1186/s12859-016-0946-4

Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on ViterbiFilter
Figure Legend Snippet: Evaluations of CUDAMPF with Intel Xeon, i5 and i7 on ViterbiFilter

Techniques Used:

Related Articles

Software:

Article Title: Pluri-IQ: Quantification of Embryonic Stem Cell Pluripotency through an Image-Based Analysis Software
Article Snippet: .. Software Availability Pluri-IQ was implemented using MATLAB on a 64-bit Windows OS laptop with intel i7 processor with 8 GB of RAM memory. .. The software will be hosted at the CNC website ( http://www.cnbc.pt/equipment/microscopyUnit.asp#divImageAnalysis ) both as a compiled MATLAB standalone application (requires installation of 64 bit MATLAB runtime, available for free at www.mathworks.com/products/compiler/mcr.html ) and MATLAB.m files.

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